Config Register

Address

0x00

Description

The CONFIG register is used to enable and disable the three interrupts that the radio can generate, configure the cyclic redundancy check (CRC) code that is appended to packets, power the radio up and down, and switch the radio between receive and transmit mode.

Contents

This table is copied from the nRF24L01 product specification (page 53).

Name
Bit
Reset Value
Type Description
Reserved 7 0 R/W Only ‘0’ allowed
MASK_RX_DR 6 0 R/W Mask interrupt caused by RX_DR
1: Interrupt not reflected on the IRQ pin
0: Reflect RX_DR as active low interrupt on the IRQ pin
MASK_TX_DS 5 0 R/W Mask interrupt caused by TX_DS
1: Interrupt not reflected on the IRQ pin
0: Reflect TX_DS as active low interrupt on the IRQ pin
MASK_MAX_RT 4 0 R/W Mask interrupt caused by MAX_RT
1: Interrupt not reflected on the IRQ pin
0: Reflect MAX_RT as active low interrupt on the IRQ pin
EN_CRC 3 1 R/W Enable CRC. Forced high if one of the bits in the EN_AA is high
CRC0 2 0 R/W CRC encoding scheme
‘0’ – 1 byte
‘1’ – 2 bytes
PWR_UP 1 0 R/W 1: POWER UP, 0:POWER DOWN
PRIM_RX 0 0 R/W RX/TX control
1: PRX, 0: PTX

Comments

The software driver sets this register to 0b00001111 by default.

The interrupts referred to above are described in the Firmware page.

The radio documentation often refers to a radio configured in receive mode as PRX (Primary Receiver) and to a radio configured in transmit mode as PTX (Primary Transmitter).  The PRIM_RX bit determines whether the radio is in receive mode or transmit mode (normally it is set to 1, and set to 0 only while the radio is transmitting).

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