Address
0x07
Description
The STATUS register is used to read the interrupt status, get the number of the pipe that received a packet, and get the Tx FIFO status.
Contents
This table is copied from the nRF24L01 product specification (page 55).
| Name |
Bit |
Reset Value |
Type | Description |
| Reserved | 7 | 0 | R/W | Only ‘0’ allowed |
| RX_DR | 6 | 0 | R/W | Data Ready RX FIFO interrupt. Asserted when new data arrives RX FIFO. Write 1 to clear bit. |
| TX_DS | 5 | 0 | R/W | Data Sent TX FIFO interrupt. Asserted when packet transmitted on TX. If AUTO_ACK is activated, this bit is set high only when ACK is received. Write 1 to clear bit. |
| MAX_RT | 4 | 0 | R/W | Maximum number of TX retransmits interrupt. Write 1 to clear bit. If MAX_RT is asserted it must be cleared to enable further communication. |
| RX_P_NO | 3:1 | 111 | R | Data pipe number for the payload available for reading from RX_FIFO 000-101: Data Pipe Number 110: Not Used 111: RX FIFO Empty |
| TX_FULL | 0 | 0 | R | TX FIFO full flag. 1: TX FIFO full. 0: Available locations in TX FIFO. |
Comments
The contents of this register are returned over SPI when an instruction byte is clocked into the radio. The NOP instruction can be clocked in to retrieve this register quickly.
The RX_DR and TX_DS interrupt bits might both be set, if the radio receives an ack packet that includes a payload. The TX_DS and MAX_RT interrupts will never be fired at the same time. The interrupt bits must be cleared manually by writing “1”s to them after the interrupts have been handled. (See this FAQ for a discussion on why interrupt bits are commonly cleared by writing “1”s to them despite the rule seeming counterintuitive at first.)
The RX_P_NO field holds the number of the Rx pipe that received the packet at the head of the Rx FIFO. When that packet is removed from the FIFO (using the R_RX_PAYLOAD instruction), RX_P_NO holds the number of the Rx pipe that received the next packet, or 111 if there are no more packets in the FIFO.
The radio driver doesn’t currently take advantage of the Tx FIFO to load multiple packets for transmission, so it doesn’t use TX_FULL.