Address
0x17
Description
The FIFO_STATUS register contains information on whether the Rx and Tx FIFOs are full or empty, and whether the radio is continually transmitting the contents of the Tx FIFO.
Contents
This table is copied from the nRF24L01 product specification (page 57).
| Name |
Bit |
Reset Value |
Type | Description |
| Reserved | 7 | 0 | R/W | Only ‘0’ allowed |
| TX_REUSE | 6 | 0 | R | Reuse last transmitted data packet if set high. The packet is repeatedly retransmitted as long as CE is high. TX_REUSE is set by the SPI instruction REUSE_TX_PL, and is reset by the SPI instructions W_TX_PAYLOAD or FLUSH TX |
| TX_FULL | 5 | 0 | R | TX FIFO full flag.
1: TX FIFO full. 0: Available locations in TX FIFO. |
| TX_EMPTY | 4 | 1 | R | TX FIFO empty flag. 1: TX FIFO empty. 0: Data in TX FIFO. |
| Reserved | 3:2 | 00 | R/W | Only ’00’ allowed |
| RX_FULL | 1 | 0 | R | RX FIFO full flag. 1: RX FIFO full. 0: Available locations in RX FIFO. |
| RX_EMPTY | 0 | 1 | R | RX FIFO empty flag. 1: RX FIFO empty. 0: Data in RX FIFO. |
Comments
The value of TX_FULL is duplicated in the STATUS register.
TX_FULL and TX_EMPTY are not exclusively opposite. For example, if the FIFO contains a single packet then it is neither full nor empty, so both fields are 0. Obviously, a FIFO can’t be both full and empty.